1. Technical Field
The present invention relates in general to testing and verification, and in particular to verification of digital designs. Still more particularly, the present invention relates to a system, method and computer program product for verification of digital designs through reconfiguration of random biases in a synthesized design without recompilation.
2. Description of the Related Art
With the increasing penetration of processor-based systems into every facet of human activity, demands have increased on the processor and application-specific integrated circuit (ASIC) development and production community to produce systems that are free from design flaws. Circuit products, including microprocessors, digital signal and other special-purpose processors, and ASICs, have become involved in the performance of a vast array of critical functions, and the involvement of microprocessors in the important tasks of daily life has heightened the expectation of error-free and flaw-free design. Whether the impact of errors in design would be measured in human lives or in mere dollars and cents, consumers of circuit products have lost tolerance for results polluted by design errors. Consumers will not tolerate, by way of example, miscalculations on the floor of the stock exchange, in the medical devices that support human life, or in the computers that control their automobiles. All of these activities represent areas where the need for reliable circuit results has risen to a mission-critical concern.
In response to the increasing need for reliable, error-free designs, the processor and ASIC design and development community has developed rigorous, if incredibly expensive, methods for testing and verification for demonstrating the correctness of a design. The task of hardware verification has become one of the most important and time-consuming aspects of the design process. In order to maximize the verification coverage attainable with the resources available to a hardware design, numerous verification methods have been developed, each with their own strengths and weaknesses. These methods include random simulation, hardware emulation, formal verification, and semi-formal verification.
The benefit of random simulation is that it may readily be deployed to attempt to find bugs in large designs, and may be run on any computer from a laptop to a workstation. A drawback of random simulation lies in the limited coverage attainable with such an “explicit search” paradigm, and that it becomes slower as the design size increases. Typically, the stimulus provided to the design in such an environment is through a high-level language which accepts some specification indicating how to generate random stimulus. The high-level specification code interprets the specification to determine how to inject values to drive the simulation process. Example high-level languages include C/C++, or SystemVerilog.
Hardware emulation environments are similar to random simulation environments in the sense that they explicitly search only one path of the design at a time (and hence have limited coverage), though they are often orders of magnitude faster in their evaluation of the design, particularly for very large designs. To enable increased speed, C/C++ interfaces are often discarded in favor of synthesized versions of the random stimulus specification.
Formal and semi-formal verification environments leverage symbolic evaluation of the design to consider astronomically large number of search paths in parallel. In some cases, formal and semi-formal verification environments are able to even complete proofs of correctness of the design, and may yield much greater coverage than random simulation or emulation environments. However, symbolic evaluation through formal and semi-formal verification environments is computationally expensive and may prove inapplicable to larger designs. To enable the symbolic search, C/C++ interfaces are discarded in favor of synthesized versions of the random stimulus specification (as with emulation environments).
These distinct verification methodologies all require that the verification engineer develop a specification for the manner in which random stimulus may be applied to the design under test. Note that there are two aspects to such a specification. First, the “constraining” aspect, which disallows “illegal” stimulus from being applied to the design and causes “false failures” must be considered in all platforms. Second, the “bias” aspect, which indicates the probability with which certain random values will be applied to the design under verification, is most important to simulation, emulation, and semi-formal frameworks. Simulation, emulation, and semi-formal frameworks are dependent upon random explicit search to expose interesting regions of behavior of the design under test. Purely formal algorithms will ignore such biases since they are (by construction) exhaustive and explore all possible stimulus.
Hitherto, the languages used to specify the “constraint” and “bias” aspects of random stimulus to be applied in the verification process (hereafter referred to as the “driver” and the “bias data”, respectively) are different in random simulation versus emulation/formal/semi-formal environments, because the former often use C/C++ interpreters whereas the latter require synthesis of this data into a netlist type of representation. The need for multiple file types creates problems by increasing the amount of manual effort needed in the overall verification process (since equivalent specifications may need to be created in two different languages), and adds risk of omissions, errors, etc. Under the prior art, a single shared specification cannot directly be used in both platforms. What is needed is method and computer program product for verification of digital designs through reconfiguration of random biases in a synthesized design without recompilation.